Conventional arrays of electrically programmable read-only memory cells (EPROMs) are formed by first implanting a plurality of elongate source/drain regions at a face of a semiconductor substrate. This substrate is then masked, and a field oxide is grown in the unmasked areas. Thereafter, a thin gate oxide is grown between the field oxide areas, and a plurality of floating gates are deposited, patterned and etched to extend over the gate oxide. A second interlevel gate oxide is grown from the floating gates, which are usually polysilicon. Thereafter, a plurality of control electrodes are deposited, patterned and etched such that each of them will extend over a plurality of floating gates in any one row.
The above-described conventional process produces an EPROM array having severe topology. The growth of a field oxide over the source/drain regions depresses them below the original surface of the semiconductor substrate. The source/drain regions are degraded because they experience several temperature cycles during the fabrication of the conventional array. These source/drain regions are therefore less efficient in the generation of hot electrons for injection through the thin gate oxide layer into the floating gate. Programming voltages must therefore be higher, in one instance approximating 14 volts. The severe topology of these conventional arrays increases the incidence of shorting metal and poly filaments and therefore decreases quality control.
From the above, it can be seen that a need has arisen in the industry for a planarized array having substantially flat topology, and further for an EPROM array wherein the source/drain regions comprising its bit lines remain disposed near the original surface of the semiconductor substrate, such that the bit lines can more efficiently generate hot electrons for programming the EPROM cell.